NOTICE: This Document was reapproved with minor editorial changes.
This Guide is intended to address the needs of the
3D Stacked IC (3DS-IC) industry by providing the tools needed to procure
processed wafers to be used in a 3DS-IC process.
This Guide provides the tools to describe individual
wafers in a 3DS-IC process. In particular, this Document provides direction for
describing the dimensions, materials, and devices for wafers that have
undergone processing and are entering 3D stacking process steps. Since a 3D
stacking process may include wafers from multiple fabrication facilities, it is
important that this information is available to ensure additional process steps
are performed correctly.
This Guide describes wafers and wafer stacks with
nominal diameter of 300 mm and nominal thickness of 775 µm, although the actual
wafer diameter and/or thickness may differ due to 3D stacking requirements
and/or the effects of prior processing steps.
Referenced SEMI Standards
SEMI M1 — Specification for Polished Single Crystal Silicon Wafers
SEMI M45 — Specification for 300 mm Wafer Shipping System
SEMI M59 — Terminology for Silicon Technology
SEMI MF534 — Test Method for Bow of Silicon Wafers
SEMI MF657 — Test Method for Measuring Warp and Total Thickness Variation
on Silicon Wafers by Noncontact Scanning
SEMI MF1390 — Test Method for Measuring Bow and Warp on Silicon Wafers by
Automated Noncontact Scanning
SEMI MF1451 — Test Method for Measuring Sori on Silicon Wafers by
Automated Noncontact Scanning
SEMI T7 — Specification for Back Surface Marking of Double-Side Polished
Wafers with a Two-Dimensional Matrix Code Symbol
